FIG. 1 shows a conventional serial backplane interface 10 for interfacing a physical (PHY) layer backplane or other circuit to a link layer in a network node or other communication device. The interface 10 includes a link layer controller 12, a backplane physical layer controller 14, and a backplane transceiver 16. The link layer controller 12 and the physical layer controller 14 operate in accordance with the Institute of Electrical and Electronics Engineers (IEEE) Standard 1394-1995 for a High Performance Serial Bus, which will be referred to simply as the IEEE 1394 standard, and is incorporated by reference herein. The IEEE 1394 standard describes a serial bus for use as a peripheral bus or a backup to one or more parallel backplane buses. The backplane transceiver 16 of serial backplane interface 10 provides an electrical/mechanical interface to a serial backplane bus 17. Bidirectional backplane strobe signals (BPstrb+ and BPstrb-) and backplane data signals (BPdata+ and BPdata-) pass between the transceiver 16 and the serial backplane bus 17. Corresponding unidirectional transmit strobe (TSTRB), transmit data (TData), receive strobe (RSTRB) and receive data (RData) signal lines pass between the transceiver 16 and the PHY layer controller 14. The transceiver 16 is often packaged separately from the PHY layer controller 14 such that different transceivers can be used for different types of serial backplane buses. The type of transceiver used determines the packet transmission rate on the serial bus 17. For example, transceivers using BTL or Emitter-Coupled Logic (ECL) transmit and receive at 49.152 MB/sec, while transceivers using Enhanced Transceiver Logic (ETL) operate at 24.576 MB/sec.
The link layer controller 12 provides acknowledged one-way data transfer services via a host interface 18 with upper layers of nodes utilizing the serial backplane bus. For example, the controller 12 responds to read/write/lock requests from the upper layers of a node implementing the serial backplane interface 10, and it prepares packets for transmission through the PHY layer and onto the serial backplane bus 17. The link layer controller 12 also responds to changes in the state of the serial bus 17 (i.e., received data packets) as indicated by the PHY layer controller 14. Other functions of the link layer controller 12 include addressing, error checking and data framing (i.e., within a given packet). Information is transmitted bidirectionally between the link layer controller 12 and the PHY layer controller 14 using a data bus 20 including data lines DATA[0:7] and a control bus 22 including control signal lines CTL[0:1]. In a typical conventional implementation, only two of the DATA[0:7] data lines, i.e., data lines D0 and D1, are used. A system clock (SCLK) is supplied from the PHY layer controller 14 to the link layer controller 12. Link requests (LREQs) are transmitted unidirectionally from the link layer controller 12 to the PHY layer controller 14 as shown.
FIG. 2 illustrates the PHY layer controller 14 of serial backplane interface 10 in greater detail. The PHY layer controller 14 performs functions such as packet reception/transmission and arbitration, and includes a LINK/PHY interface 30, an arbitration control block 32, a data encode block 34, an arbitration/data multiplexer 36, and a data resynchronize/decode block 38. A reference clock (CLK) is used to provide synchronization of various state machines within the PHY layer controller 14. The frequency of this reference clock is 49.152 MHz (.+-.100 ppm), regardless of the data transmission rate. The above-noted SCLK is derived from the reference clock. The four basic operations that can occur between the link layer controller 12 and the PHY layer controller 14 are request, status, transmit and receive, and all but the request operation are initiated by the PHY layer controller 14. The link layer controller 12 uses the request operation to read or write an internal PHY register or to request the PHY layer controller 14 to initiate a transmit operation. The PHY layer controller 14 initiates a status operation whenever the status of the serial bus 17 changes.
The PHY layer controller 14 initiates a transmit operation in response to a request from the link layer controller 12. The data bits to be transmitted are received over the data lines 20 from the link layer controller 12. These data bits are latched in the data encode block 34 of controller 14 in synchronization with the system clock SCLK, combined serially, encoded, and then transmitted by the arbitration/data multiplexer 36 on the TData line to the transceiver 16. The corresponding strobe information is transmitted by the arbitration/data multiplexer 36 on the TSTRB line to the transceiver 16. The PHY layer controller 14 initiates a receive operation whenever a packet is received on the serial bus 17. The packet data is received in the data resynchronize/decode block 38 on the RData line and the corresponding strobe information is received in block 38 on the RSTRB line. The received data-strobe information is decoded in block 38 to recover the receive clock (RxCLK) and the serial data bits. The serial data bits are then resynchronized to the local system clock, separated into two parallel streams, and sent to the associated link via LINK/PHY interface 30. Additional details regarding the operation of the various elements of the PHY layer controller 14 of FIG. 2 can be found in the above-referenced IEEE 1394 standard document. A typical commercially available PHY layer controller is the TSB14C01 5-V IEEE 1394-1995 Backplane Transceiver/Arbiter from Texas Instruments Inc. of Dallas Tex.
A significant problem with the conventional IEEE 1394 serial backplane interface 10 described in conjunction with FIGS. 1 and 2 above is that its data bandwidth is unduly limited. For example, the serial backplane interface 10 supports a serial backplane data bus 17 which is always only a single data bit wide. In other words, the conventional PHY layer controller 14 and the transceiver 16 as shown in FIGS. 1 and 2 are configured to process one data bit at a time. This limits the data transfer rate through the interface 10, and hence its effective data bandwidth, while also preventing the corresponding network node or other communication device from taking full advantage of the performance capabilities of its link layer circuitry. Increasing the data bandwidth in the conventional serial backplane interface 10 generally requires increasing the PHY layer clock frequency, which may not be a practical or desirable approach in a given application. A need therefore exists for an improved backplane PHY layer interface in which the effective data bandwidth can be increased without requiring a corresponding increase in the PHY layer clock frequency, while also maintaining compatibility with the basic IEEE 1394 serial bus architecture.